The present invention relates generally to integrated circuits (ICs), and more particularly to a dual voltage single gate oxide input/output (I/O) circuit with high voltage stress tolerance.
Devices in different IC packages are interconnected to one another at I/O pads that interface with various electrical circuits performing certain functions. It is common for such interconnected circuits to utilize standard voltage levels for representing logic states of “0” and “1.” Common standard voltage levels in the past have been set to 0 V for representing zero logic state and 5V for representing the one logic state. As new IC manufacturing technologies evolve, the voltage levels used to represent a logic one state have been reduced to, for example, 3.3V, 2.5V, or 1.8 V. The lower voltage levels permit reduced thickness in the gate oxide of transistor, thereby reducing the transistor switching time and power consumption. However, as IC design quickly migrates to the lower voltage realm, some peripheral components still operate with the higher voltages such as 3.3V and 5V. As a result, a system often includes circuits that operate at different voltages.
A metal-oxide-semiconductor (MOS) transistor is typically composed of a conductor, insulator, and semiconductor. When a voltage is applied to the conductor of the MOS transistor, a depletion region is formed under the insulator in the semiconductor. When the applied voltage is increased to a certain level (threshold voltage), a conductive channel is created in the semiconductor between source and drain regions. When the applied voltage further exceeds a certain level (breakdown voltage), it can cause the insulator to break down, and the MOS transistor to fail.
In a system having circuits operating with different voltages, an I/O circuit is typically used to interface these circuits in order to prevent the devices in the low voltage circuit from damage induced by the high voltage of another circuit. Conventionally, the gate oxide of the MOS transistor in the I/O circuit is thicker than that of the devices in other circuits for withstanding high voltage inputs. This is the so called dual gate oxide technology. However, the main drawback of the dual gate oxide technology is that two separate sets of masks are required for the thick and thin oxide MOS transistors. This increases the manufacturing costs and decreases the product yield rates.
As such, what is needed is an I/O circuit constructed by single gate oxide technology with high voltage stress tolerance.